Code :

---

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY antirebon IS
PORT(BP, clock_100Hz : IN STD_LOGIC;
BP_antirebon : OUT STD_LOGIC);
END antirebon;

ARCHITECTURE a OF antirebon IS
SIGNAL SHIFT_BP : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
process
begin
wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1');
SHIFT_BP(2 Downto 0) <= SHIFT_BP(3 Downto 1);
SHIFT_BP(3) <= NOT BP;
If SHIFT_BP(3 Downto 0)="0000" THEN
BP_antirebon <= '0';
ELSE
BP_antirebon <= '1';
End if;
end process;
end a;